The story behind this piece
Logica draws a 4-bit ripple-carry adder built from four full adders, each made of two XOR gates, two AND gates and an OR gate in standard ANSI shapes. Every stage computes S = A ⊕ B ⊕ Cin and Cout = A·B + Cin·(A ⊕ B), then hands its carry to the next. The plate is frozen mid-sum: A = 1011 (11) plus B = 0110 (6). Each wire is coloured by the level it would really carry, vermilion for 1 and ink for 0, so you can follow the carry rippling from bit 1 to the output: 1 0001, or 17. The truth table, Karnaugh maps and gate-delay count below come from the same logic.


