The story behind this piece
Silicio imagines the die photograph of a modern system-on-chip, in the false colour that makes these images so loved. It copies no real chip, but its floorplan follows real practice: four performance CPU cores with private L2 and a shared L3, a cluster of small efficiency cores, eight identical GPU shader cores around a GPU cache, an NPU of repeated multiply-accumulate tiles and a large system cache. SRAM shows as regular grids with decoder spines, synthesised logic as finer mottled texture. Memory and PCIe PHYs line the edge inside a ring of I/O cells, bond pads and a seal ring, under a clock H-tree.
